A SRAM has been used as a cache memory used for a personal computer and a work station.
The SRAM comprises a flip-flop circuit for storing one-bit information therein and two information transfer MISFETs (Metal Insulator Semiconductor Field Effect Transistors). The flip-flop circuit comprises, for example, a pair of driver MISFETs and a pair of load MISFETs.
A problem associated with a soft error produced due to an α ray arises in each memory cell of such a memory. The soft error produced due to the α ray is a phenomenon in which an α ray contained in external cosmic radiation, or an α ray emitted from a radioactive atom contained in a package material for an LSI enters a memory cell and damages or corrupts information stored in the memory cell.
In order to take measures against such an α ray, a method has been discussed which adds capacitance to an information storage unit (corresponding to an input/output part of the flip-flop circuit) in the memory cell to thereby increase the capacitance of the information storage unit.
A technology for forming a capacitor or capacitance by polycrystalline silicon 10 connected to drain regions of FETs Qp′ and Qnd′, and polycrystalline silicon 11 connected to drain regions of FETs Qp and Qnd to thereby improve resistance to a soft error has been described in Unexamined Patent Publication No. Hei 11(1999)-17027, for example.
Further, there is disclosed in Unexamined Patent Publication No. Hei 10(1998)-163440 a technology for constituting a capacitor C by local wirings L1 and L2 at which input/output terminals of a flip-flop circuit for storing information therein are cross-connected, and a thin insulating film interposed between the two thereby to increase the capacity of a storage node of each memory cell, thus preventing a reduction in resistance to an α ray-based soft error.
However, with advances in memory cell scale-down incident to high integration of each memory cell, an area where the capacitance can be formed, also decreases. Thus there is a limit to increase the capacity of the information unit.
On the other hand, targeted values for capacitance also increase according to intended purposes of products. FIG. 48 is a diagram showing the relationship between incident energy (MeV) of α rays to a product having a power supply voltage (Vcc) of 1.2V and a product having a power supply voltage (Vcc) of 1.5V, and the amount of noise charges (C). As shown in FIG. 48, an electrical charge (noise) is stored in an information storage unit when the α ray is applied to the information storage unit. The maximum value of the charge results in 6.2 fC in the case of the 1.2V product. Since the critical amount of charge for this product is given as 4.3 fF, it is necessary to add a capacitor or capacitance capable of storing a charge amount of 1.9 (=6.2−4.3) fC or more to each node. Since the maximum value of the charge is 6.1 fF and the critical amount of charge is 3.4 fC in the case of the 1.5V product, it is necessary to add a capacitor or capacitance capable of storing a charge amount of 2.7 (=6.1−3.4) fC to each node. Incidentally, the critical amount of charge indicates the amount of an electrical charge which inverts information (1 or 0) held in the information storage unit.
The required capacitance is becoming great despite of the reduction in the capacitance-formable area with the scale down of each memory cell.
An object of the present invention is to provide a semiconductor integrated circuit device, e.g., a technology for ensuring the capacitance of an information storage unit of each memory cell in a SRAM to thereby make it possible to reduce a soft error produced due to an α ray.
Another object of the present invention is to provide a semiconductor integrated circuit device, e.g., a semiconductor integrated circuit device that reduces a soft error produced in each memory cell of a SRAM.
The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.